Free winboard pcb software for linux

XBoard project is a X and Windows graphical chessboard.
XBoard is a graphical chessboard for X that can serve as a user interface for GNU Chess, Crafty, other chess engines, and the Internet Chess Servers.
XBoard can also be used by itself to read and write game files in PGN (portable game notation). WinBoard is a port of XBoard to Microsoft Win32.
You can build xboard on most systems with the following commands.
./configure
make
Enhancements:
- Version 4.2.7 corrects about two dozen bugs in the 4.2.6 release.
- In addition, WinBoard 4.2.7 comes bundled with GNU Chess 5.07 instead of the old 5.02+ version.
- The XBoard and WinBoard source code trees have been merged, so the xboard download now contains the complete source for both.

Tiffanys project is a Java chess engine, including a Swing gui and Win/XBoard support.
It supports the PGN / FEN format. Tiffanys also contains a XBoard / Winboard interface.
Main features:
- Swing GUI
- PGN / FEN Support
- XBoard interface
- Knows all basic rules (including Castling, EnPassant and Pawnpromotion)

Videoconv is a shell-based frontend to mpeg-tools, transcode, vcdimager, and cdrdao. This script converts AVI videos to VCD, SVCD, or DivX, and optionally burns them to CD. The script was designed to allow even unexperienced users to convert videos.
It is only a simple frontend to mjpeg-tools and transcode.But you will need these helpful tools:
mjpegtools (Converting)
transcode (DIVX)
videocodecs you want to use with transcode (divx5, opendivx and xvid)
vcdimager (what may this be for ?)
cdrdao (burning)
Youseful but not mandatory, versions may be higher:
divx4linux
libdvdcss2
libdvdread
libfame
win32-codecs
xvid
Enhancements:
- Quality of the generated videos was improved
- Added support for multipassencoding with divx
- PCB-Menusupport added for VCD und SVCD with vcdxgen
- Changed $ to * for the wildcard in the vcdxgen part. This should fix the error with the vcdmenuecreation
- Added option -x to transcode, because autodection of some avifiles failed
- Some minor bugfixes

Dolphin Smash is a mixed-signal, multi-language simulator for IC or PCB designs. Dolphin Smash extends its capabilities for mixed signal code-coverage and sensitivity-analysis up to detecting flaws in Virtual Testbenches and to identifying circuit weaknesses for the DfM conscious designer.
Improvement on the block-busting GUI features facilitate further the adjustments of speed versus accuracy, as well as tracing, now augmented for a hierarchical view applicable to mixed signal design.
Main features:
- Code coverage for HDL-AMS
- DC & small-signal dispersion sensitivity analysis
- Power consumption estimation after Place & Route with SPEF back-annotation
- Enhanced GUI with tree view selection of traces and interactive logging panes
- BSIM4v5 update including a well proximity effect model
- CSDF and VCD output formats for exporting of analog and logic simulation results
- VDA automotive libraries bundled
With analysis of sensitivity to dispersion, SMASH provides a fast and accurate solution for the problems of design for yield, manufacturability and robust design of nano-electronic analog circuits. Compared to Monte Carlo analysis, the sensitivity to dispersion is thousands of times faster. Furthermore, the sensitivity to dispersion analysis provides the contribution of each component to the total dispersion, thus design debugging becomes trivial.
As SCROOGE enables power consumption analysis before Place & Route, the SPEF back-annotation now provides it with parasitic capacitance back-annotation for an accurate power consumption analysis after Place & Route. Parasitic capacitances are taken into account to back-annotate the Liberty wire load model. This allows to consider the exact routing capacitance both for cell interconnection wires and for clock trees, which represent an important part of the consumed power.
For increased interoperability, simulation results can now be exported into standard VCD (Verilog Change Dump) format for logic or CSDF (Common Simulation Data Format) for reuse in all compatible EDA solutions. Of course, SMASH can also import and display VCD or CSDF results as well as.
Enhancements:
- The release delivers an interactive debugger with break points, step by step and event back trace for source level debugging of HDL-AMS descriptions, phase-noise extraction on long term Jitter, a SPICE inductance model with magnetic core as well as cosimulation of analog and mixed-signal blocks with MATLAB/Simulink.

LedaX is ment to be an EDA including a Library Editor, Schematic Capture and PCB Editor.
LedaX will consist of a minimum of 3 applications, as mentioned above. There has been a lot of talk about having one application for all, but as I see it, why not make use of Xs ability to have more than one desktop.
We might make plugins for autoplacement and auto arrangement for the PCB editor, but again this is for later plans.
We WILL try to make it work with as many application around for Linux. I.e. ktechlab, gEDA etc.
The storage for the system is a MySQL database. This means that several people can work on one project at a time.
Enhancements:
- Lots and lots of cleanup done by Alain.
- Also a lot of functinality completion and bugfixes done by Alain.

Chessweb is a J2EE chess game Website. It is a pure Java servlet implementation of a two-player chess game.

Two players log into the Web site, see an image of the current board in their browser, and make their moves.

The differentiating features of chessweb (e.g. versus WinBoard / XBoard) is that its an extremely lightweight implementation written completely in Java (nothing more than an app server and browser is required).

Furthermore, the client end is DHTML only, and verified to works with FireFox 1.0.6 and IE 6.

HDLmaker is a tool for generating Verilog designs. HDLmaker simplifies the development of complex FPGA designs as well as PC Boards by performing the following tasks:
- Writes hierarchical Verilog code
- Generates retargetable IO pad rings
- Generates all of the necessary scripts and Make files
- Supports mulitlanguage projects
- Converts PCB net lists into VHDL and Verilog
- Generates SCALD and PADS PCB board netlists
- Generates Schematics in Postscript format
- Designs are portable between FPGA families and CAE tools
- Simplifies the reuse of HDL code
- Converts HDLmaker, Verilog and VHDL files into fully hyper linked HTML
Main features:
- Writes Hierarchical Verilog.
- Output can be targeted to either Verilog or VHDL (VHDL support has been deprecated).
- Supports mixed language development.
- Generates PC board netlists in both PADS PCB and SCALD formats.
- Generates Schematics in Postscript format.
- Supports the most popular FPGAs
- Xilinx Virtex4,Virtex2P, Virtex2,VirtexE,Virtex, Spartan3, Spartan2,4000E,4000EX,4000XL,5200,9500, Altera Stratix
- Supports the most popular synthesizers
- Synplify
- Xilinx XST
- Altera
- Synopsys Design Compiler
- Precision
- Supports most simulators
- Fintronics Finsim
- Cadence Verilog XL
- Cadence NC-SIM
- Model Technologies (VHDL and Verilog)
- Synopsys VCS
- HTML Generation
- HDLmaker generates an HTML version of the design with hyper links from all source files to generated files and from all component instances to the components module. Verilog and VHDL HTMLized are also syntax colored.
Enhancements:
- insert_compare, Inserts a module with a compare wrapper around it
- Added HDLMAKER_ALLOW_SUB variable
- Added xst_directive
- Floorplanning support for Multipliers and Block RAMs
- New XST constraints
- Improved DDR IO support including differential DDR
- Improved Xilinx project support
- Virtex4 Support
- Better ModelSim support. Creates three command files, foo_compile_mt.cmd to compile the modules, foo_i_mt.cmd for interactive use, and foo_batch_mt.cmd for batch simulation.
- Initial values of HDLmaker variables can be passed in from the command line or from a file
- Better comment support
- More flexible #clock statement
- Comments in pin files
- Support for Xilinx ISE 6.1
- Support for Virtex2P
- Support for Precision and ModelSim added
- Large Project Support, HDLMaker now operates across multiple directories
- Virtex2, Spartan2 and Spartan2E support added
- Altera Stratix support added
- Multilanguage project support. Can embed VHDL entities into Verilog files and Verilog modules into VHDL files.

Gullydeckel Chess Program project is a simple chess program.
The Gullydeckel chess playing program allows you to play a game of chess against a not too strong opponent. It has been written by Martin Borriss and is available free of charge on the terms of the GNU General Public License (GPL).
You can use Gullydeckel with Linux and Windows. Most people integrate Gullydeckel with a graphical chess board such as WinBoard. Other interfaces are quite possible (Fritz 8, Arena, or Chessbase).
Installing
1. Extract the sources from the archive (e.g., "tar zxf g2_2.13.pl6.tgz")
2. "cd src"
3. "make" (This gives you the gully2 binary.)
4. To have the opening book available, copy the file "book.bin" into the directory where the binary resides. (This is the place and filename searched by default.)
5. Now you are ready to go. You can solve testsuites (in epd/fen format) by typing something like
"gully2 -f ../Tests/bk.epd --time 30"
or play a game using Xboard (e.g., "xboard -fcp gully2").
Enhancements:
- This release removes extra polling code used when pondering structures for detailed evaluation in place.