Free vhdl software for linux

Hardware::Vhdl::Lexer is a Perl module that can split VHDL code into lexical tokens.

SYNOPSIS

use Hardware::Vhdl::Lexer;

# Open the file to get the VHDL code from
my $fh;
open $fh, new({ linesource => $fh });

# Dump all the tokens
my ($token, $type);
while( (($token, $type) = $lexer->get_next_token) && defined $token) {
print "# type = $type token=$tokenn";
}

Hardware::Vhdl::Lexer splits VHDL code into lexical tokens. To use it, you need to first create a lexer object, passing in something which will supply chunks of VHDL code to the lexer. Repeated calls to the get_next_token method of the lexer will then return VHDL tokens (in scalar context) or a token type code and the token (in list context). get_next_token returns undef when there are no more tokens to be read.

NB: in this documentation I refer to "lines" of VHDL code and "line" sources etc., but in fact the chunks of code dont have to be broken up at line-ends - they can be broken anywhere that isnt in the middle of a token. New-line characters just happen to be a simple and safe way to split up a file. You dont even have to split up the VHDL at all, you can pass in the whole thing as the first and only "line".

Hardware::Simulator is a Perl extension for Perl Hardware Descriptor Language.

SYNOPSIS

use Hardware::Simulator;

# NewSignal( perl_variable [, initial_value]);
# create a signal called $in_clk, give it an initial value of 1
NewSignal(my $in_clk,1);

# Repeater ( time_units , code_ref)
# every time_units, call the code reference, starting at the current time
Repeater ( 5, sub{if ( $in_clk==0) { $in_clk=1;} else { $in_clk=0;}});

# Responder ( [signal_name ... signal_name], code_ref );
# respond to any changes to signals by calling code reference.
# any time out_clk changes, print value of clock and simulation time.
Responder ( $out_clk, sub
{
my $time = SimTime();
print "out_clk = $out_clk. time=$timen";
});

# start processing of events and event scheduling.
EventLoop();

Hardware::Simulator ==> a Perl Hardware Descriptor Language

Hardware::Simulator is a lightweight version of VHDL or Verilog HDL. All of these languages were developed as means to describe hardware.

Hardware::Simulator was created as a means to quickly prototype a basic hardware design and simulate it. VHDL and Verilog are both restrictive in their own ways. Hardware::Simulator was created to quickly put something together as a "proof of concept", to show that a design concept would work or not. and then the design could be translated to VHDL or Verilog.

The problem that started all of this was designing a fifo for a video scaling asic. The chip used a buffer to store incoming video data. The asic read the buffer to generate the outgoing video image. We estimated how large we thought the buffer needed to be, but we wanted to confirm that our numbers were right by running simulations.

The problem was we needed to run hundreds of different simulations, given the permutations of input image formats, output image formats, and input/output clock frequencies. We also had text files containing valid formats and frequencies. A text file as input called for perl to manipulate, split, format, and extract the data properly.

This data then had to be translated onto the a HDL simulation. The problem was that there was no easy way to write a perl script that would simulate hardware, so the only solution was to have perl drive a Verilog simulator and pass all these parameters via command line parameters. so then verilog files had to be created, and the simulator had to be driven, and the end result was a lot of work to simulate a simple fifo.

Time contraints did not allow me to develop a HDL package for perl to solve the original problem, but I took it on in my spare time. and eventually Hardware::Simulator was born.

Schifra is a very robust, highly optimized, and extremely configurable Reed-Solomon error correcting code library for both software and IP core based applications with implementations in C++ and VHDL.
The project supports standard, shortened, and punctured Reed-Solomon codes. It also has support for stacked product codes and interleaving.
Schifra provides a concise, predictable, and deterministic interface which lends itself to easy and seamless integration into the development of complex data communication projects requiring Reed-Solomon error correcting code capabilities.
Main features:
- Errors and Erasures
- Supported Symbol Sizes - 2 to 32 bits
- Variable Code Block Length
- User defined primitive polynomial and finite field
- Accurate and Validated Reed-Solomon Codecs - Complete combinatorial errors and erasures unit testing
- Supported Architectures For Optimizations - x86-32, x86-64, PowerPC, m68k, XScale
- Supported Reed-Solomon Codes - Intelsat 1-4, DVB(S and T), MPEG-2 TSP, VDL Mode 2-4, CCSDS (Basis transform), CIRC, ETS 300-421, ETS 300-429, xDSL, PostBar, MaxiCode and many more...
- Supported Decoding Methods - Berlekamp-Massey, Berlekamp-Welsh and Sudan list decoding
- Shortened and Punctured Reed-Solomon Codes - IEEE 802.16d standard
- Product Codes
- Interleavers
- Maximum-likelihood Estimation Decoder - Beyond correcting boundry error recovery
- Optimized Encoder and Decoder - SSE1-3 and AltiVec instruction sets
- Special Optimized Decoder - For cases of 2t = 2, 4, 6, 16 and 32
- Supported Xilinix Hardware - Virtex-II, Virtex-II Pro, Spartan-3, Spartan-3E, Virtex-4
- Supported Altera Hardware - ACEX, Mercury, Stratix, Stratix GX, Cyclone
- DO-178B Level A Certified Reed-Solomon Codec - RTCA DO-224A for VDL mode 2 and 3

GTKWave is VCD/EVCD/LXT/Synopsis .out format electronic waveform viewer built using the GTK+ toolkit.

The project was originally developed by Tony Bybell but development has now passed to the APT group and we hope to extend and improve GTKWave to support new formats and features.

Installation

1) Type ./configure
2) make
3) make install (as root)

Make sure you copy the .gtkwaverc file to your home directory or to your VCD project directory. It contains the prefs for a good configuration that most people find ergonomic.

Note that Ver Structural Verilog Compiler AET files are no longer supported. They have been superceded by LXT. Also note that the AMULET group will be taking over maintenance of the viewer effective immediately.

Alliance is a complete set of free CAD tools and portable libraries for VLSI design. Alliance CAD System includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools.
A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).
Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.
Alliance provides CAD tools covering most of all the digital design flow:
- VHDL Compilation and Simulation
- Model checking and formal proof
- RTL and Logic synthesis
- Data-Path compilation
- Macro-cells generation
- Place and route
- Layout edition
- Netlist extraction and verification
- Design rules checking

Signs is a tool for logic synthesis and gate level simulation. Signss project main features include synthesis of RTL-style VHDL circuit descriptions and a dynamic graphical netlist viewer.
Supported formats include VHDL, ISCAS, and limited support for BLIF, Verilog, and EDIF netlists. Various true value and fault simulators and a combinational ATPG are included for circuit testing.
Aside from GUI mode, Signs has a pure command line mode and is fully scriptable in JavaScript and Ruby.
Main features:
- Written in Java, therefore platform-independent
- Aims to be VHDL93 compliant, at the moment a VHDL Subset is supported
- (Limited) support for non-synthesizable VHDL code, useful for testbenches
- Synthesis of RTL-style sequential VHDL process descriptions according to IEEE Std 1076.6
- Dynamic graphical netlist viewer supporting annotations (signal/gate names, signal values provided by simulators, faults)
- VHDL netlist output to file
- Input and output of netlists in ISCAS benchmark format
- Gate level true value simulators: event-based (any circuit), bit-parallel (combinational circuits only)
- Fault simulators: PPSFP, simple single faultsim
- Input and output of pattern lists in WGL format
- ATPG for combinational circuits: Implication-Graph based, PODEM
- Limited support for Verilog and EDIF netlists
- Fully scriptable in Rhino: JavaScript for Java and JRuby
- Pure command-line mode available besides GUI mode
- Integrated environment including source code and netlist structure tree views, build system, compilers and editors with syntax highlighting
Enhancements:
- While the release focus is clearly on bugfixes, there are also some feature improvements, such as enhanced test bench support and improved netlist and simulator views.
- The VHDL compiler has support for subprograms now and elaboration of big designs is much faster because of improved context handling.
- Internally, the intermediate representation layer was cleaned up, so intermediate objects form a proper tree now.

Qfsm project is a graphical editor for finite state machines written in C++ using Qt the graphical Toolkit from Trolltech.
Finite state machines are a model to describe complex objects or systems in terms of the states they may be in. In practice they can used to design integrated circuits or to create regular expressions, scanners or other program code.
Main features:
- Drawing, editing and printing of diagrams
- Binary, ASCII and "free text" condition codes
- Multiple windows
- Integrity check
- Interactive simulation
- AHDL/VHDL/Verilog HDL/KISS export
- State table export in Latex, HTML and plain text format
- Ragel file export (used for C/C++, Java or Ruby code generation)
Enhancements:
- English user documentation was written.
- The possibility of default transition was introduced.
- Ragel file export was added.
- The input condition "any" was introduced.
- The possibility to invert transition conditions was introduced.
- More arrow types were added.
- The "Free Text" type was added.
- The "print header" option was added.

Qucs project is going to be an integrated circuit simulator which means you will be able to setup a circuit with a graphical user interface (GUI) and simulate the large-signal, small-signal and noise behaviour of the circuit. After that simulation has finished you can present the simulation results on a presentation page or window.
- Qucs, briefly for Qt Universal Circuit Simulator, is a circuit simulator with graphical user interface. The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter, harmonic balance analysis, noise analysis, etc.
- Qucsator, the simulation backend, is a command line circuit simulator. It takes a network list in a certain format as input and outputs a Qucs dataset. It has been programmed for usage in the Qucs project but may also be used by other applications.
For people who are familiar with such simulators they should remember ADS from Agilent Technologies, Microwave Office from AWR and all the other simulators.
Enhancements:
- This release comes with a translation into Ukrainian, a selectable preprocessor in the SPICE component, and two new components (exponential voltage and current source).
- Libraries can now contain analogue as well as digital subcircuits.
- Analogue modelling is substantially strengthened by symbolically defined devices.
- The list of available functions in the equation solver has been extended to support more functions, logical and rational operators, and the ternary ?: construct.
- Pure digital simulations can be also performed by Verilog-HDL as an alternative to VHDL.