Free spice software for linux

Ngspice is both the name of a development project and the name of the developed software (hmm, strange isntit ?).
The ngspice project aims to build an open source GPLed mixed-mode/mixed-level circuit simulator. This means that the circuit simulator has to be written nearly from scratch, which is a complex and time consuming task.
The project first step (and not a small one) has been to get a freely available (but not GPLed) circuit simulator, spice 3f5 and studied its code in the hope that we could use it as a base for the real ngspice (the GPLed one).
While it is not possible, at the time this page is written, to base our code on spice 3f5, because of a conflict between its license and the GPL, we are trying to correct its bugs and make some improvements, providing our results to the community.
This process goes in parallel with the task of writing the new simulator. We hope that Berkeleys people will change spices license releasing it under GPL or under the new version of the BSD which has the incompatibility removed. This will surely speed up the coming of the real ngspice.
Main features:
- Better convergence: new algorithms for Operating Point analysis. Modified Fixed Point homotopy is a good candidate.
- Dynamically Loadable Devices: In the original spice code all devices models have to be statically linked in the simulator executable. This new approach will reduce the memory needed by the simulator code and improve its modularity. A device interface that allows dynamic loading has not yet defined. Since ng-spice-rework-10 all devices are shared libraries, but they must still be linked at compile time. The next step is to make devices behave as "plugins".
- Implementation of new analyses: ngspice should become a powerful synthesis tool, so 2-ports networks analyses are a must and optimization features must be taken into account.
- Mixed Mode / Mixed Level simulation: include into ng-spice the capabilities to simulate analog and digital systems and include numerical devices into its netlists. CIDER device simulator (always from Berkeleys CAD group) is the candidate for the Mixed Level part.
- Input/output enhancements: most spice users have requested improvements in the I/O part of spice, mostly compatibility issues with existing commercial simulators.
Enhancements:
- Bug fixing: most of the bugs that affected rework-15 have been fixed, thus ngspice is more stable, especially the xspice extension, the subcircuit (X devices) handling and the numparam library.
- New features: netlist syntax has been expandend allowing for end-of-line comments. A ".global" card has beed added to define global nodes, i.e. nodes that are not expanded in subcircuits. It is possible to define TC for resistors on the instance line. The editline library can be used instead of readline (no more GPL license violation).
- Porting: ngspice now works (with xspice extension) on Windows using MINGW/MSYS.

Eispice is a ground-up re-write of the Berkley Spice 3 Simulator targeted to PCB level simulation. Eispice runs in batch-mode only (i.e. no nutmeg) and doesnt include a plot utility. I use the original nutmeg but any plot utility that can read rawspice files will work (i.e. gwave).
I had two primary motivations for starting this project. I have been using Berkley Spice 3 to do PCB level SI simulations but found it a little slow. Eispice should run faster for most sims, mainly because the SuplerLU matrix library is faster than spices Sparse Matrix library.
I also wanted to add direct ibis support to spice but when I started working through the source code I came to the conclusion that it may be easier to start from scratch. So many global variables...
The current release is an alpha release. It doesnt contain all of the features that Id like it to contain, it may be unstable, it may not even compile on your machine.
Main features:
- Operating Point Analysis
- Transient Analysis
- CCVS, CCCS, VCVS, VCCS models
- I, V models
- R, L, C models
- T -- lossless transmission line model
- B -- non-linear current and voltage source models
Enhancements:
- The performance of the PyB model was greatly improved for this release.
- PyB error messages have been improved, and there is a handful of other minor bugfixes.
- This release also coincides with the release of a new eispice IDE (eide), which includes a simple PyQt based test editor, a Python Interpreter, and eispice rolled into a single application using pyinstaller.
- It is primarily intended for Windows users.

ASCO aka A SPICE Circuit Optimizer project aims to bring circuit optimization capabilities to existing SPICE simulators.
Main features:
ASCO is the result of an academic research which in itself did not intended to create a new tool, but only to design high performance analog low-power low-voltage circuits for mobile communications. Interaction with other experienced designers has resulted in the ideas existing in the ASCO tool. With the exception of the DE optimizer all code has been personally written. The key features of the ASCO tool are:
- Simulator independent: currently out-of-the-box support for Eldo (TM), HSPICE (R), LTSpice (TM) and Spectre (R) exist. More are to be included in future releases.
- Number of variables: there is, in theory, no limit to the number of circuit variables that can be optimized, except those constraints imposed by the available computer memory and/or the time required to generate a functional circuit. It is currently hardcoded in the C code.
- PVT corners: by using the simulator functionality, the possibility to test various design corners and Monte Carlo analysis is only limited to the simulator capability and by the time it takes to finish the optimization.
- Efficiency: the optimization algorithm features a global optimization using differential evolution. It has been used on a variety of applications and is know to produce good results in an acceptable time.
- Within the supported SPICE simulators, arbitrary netlist can be optimized on different conditions without having to recompile the code.
- File format: all outputted data and log information is stored in plain text format. This guarantees that they will be always readable in the future. In addition, it makes possible to use other existing tools to post-process the optimization results.
- Its free software: the code is available under the GNU GPL license.
ASCO has been designed to address problems that are particular of electric circuits. Although not limited, some possible applications can include:
- Fully redesign a new circuit described in a SPICE netlist.
- Reuse, optimize an existing circuit.
- Migrated an existing and working design to a more advanced semiconductor technology process effortlessly.
- Increase the robustness and yield of an already designed circuit by guaranteeing that it comply with all design goals and constraints in some/all process corners at will.
- Easily explore a new operating point (design space) for an already existing topology, to reduce power consumption, area or both.
- Look for a feasible new design topology before investing a considerable time trying to derive equations that describe its operation.
- Refer to Chapter 5 for ready to use practical examples to introduce you to ASCO, a SPICE circuit optimization tool. Bellow is a list of the examples that can be found with the objective of introducing the tool, its usage and applications.
- Optimization from scratch a digital inverter circuit to achieve minimum power consumption while fulfilling the design constraints; guarantee that this is valid for different process corners and also take into account device parameter mismatch (Monte Carlo).
- Optimization of a three stage operation amplifier featuring the frequency compensation technique described in [Ram05]. A total of 21 variables and five constraints/performance goals are used with the objective of obtaining the most power efficient circuit.
- The simple class-E amplifier intended for operation in the GSM-850 band is given. A more realistic model representing a differential two stage power amplifier, including all relevant circuit and board parasitics to better describe the circuit measurement performance alongside with measurements from a manufactured chip in a 0.35 um CMOS commercial technology, is given in [Ram05].
Enhancements:
- Improvements were made in the RF module functionality.
- Support was included for logarithmic search space for the existing variables.
- Code refinements and bugfixes were made.

Sub::Curry is a Perl module to create curried subroutines.

SYNOPSIS

use Sub::Curry;
use Sub::Curry qw/ :CONST curry /; # Import spice constants
# and the &curry function.

#my $f1 = Sub::Curry::->new(&foo, 1, 2); # Same as below.
my $f1 = curry(&foo, 1, 2);
my $f2 = $cb1->new(3, 4);

my $f3 = curry(&foo, 1, HOLE, 3);
my $f4 = $f3->new(2, 4);

$f1->(a); # foo(1, 2, a);
$f2->(a); # foo(1, 2, 3, 4, a);

$f3->(a); # foo(1, a, 3);
$f4->(a); # foo(1, 2, 3, 4, a);

$f4->call(a); # Same as $cb4->(a);

Sub::Curry is a module that provides the currying technique known from functional languages. This module, unlike many other modules that borrow techniques from functional languages, doesnt try to make Perl functional. Instead it tries to make currying Perlish.

This module aims to be a base for other modules that use/provide currying techniques.

This module supports a unique set of special spices (argument features). It doesnt just support holes, but also introduces antiholes, blackholes, whiteholes, and antispices. All these extra special spices effect how the spice is applied to the subroutine. They make functions such as &rcurry superfluous. See "Currying" and Sub::Curry::Cookbook.

An oft-missed feature is argument aliasing. This module preserves the aliasing.
Sub::Curry does explicit currying. For more automatic ways to use currying, look in the Sub::Curry::* namespace.

When version hits 1.00 the interface will be stable.

BitAnarch provides a BitTorrent client with many useful features and reduced resource usage.
BitAnarch is a compact BitTorrent client.
Main features:
- available in three languages
- multiple downloads support
- automatic bandwidth distribution
- full Unicode filename support
- newsgroup scanning
- automation
- drag-and-drop support
Enhancements:
- Bugfix: crashes at program termination/when the machine is very busy
- Bugfix: Error message does not appear in non-English language settings
- Silent allocation for NTFS
- Stability greatly increased
- CPU usage greatly decreased when minimized
- System newsreader is now used to view nntp messages
- The "Stay on top" setting now effects immediately, restart is no longer needed
- Download rate limit
- A spiced up user interface

My Classifieds is a web-based implementation of online classifieds, similar to other classifieds or auction sites.
It displays all aspects of the classifieds and creates all of the files for you.
Admin just needs to specify the categories, colors, template, and a few other site-specific variables and preferences.
This is done through an intuitive manage script. The script supports email and deletion/modification of ads by users, as well as searching ads, and auto-delete after an admin-specified number of days.
The admin can also delete or edit ads, delete or ban users, and change users passwords.
My Classifieds also has an intuitive language module that is easy to edit.
Already supported are English, Spanish, Puerto Rican Spanish, Norwegian, Portuguese, Danish, and Dutch. Also available: MySQL version.
Main features:
- Post an unlimited number of ads.
- Admin can allow or disallow uploading of pictures and linking to pictures.
- Admin can specify how long an ad can remain before being automatically deleted, or specify forever.
- Admin can specify categories for the ads.
- Admin can delete users, ban users, and change users passwords.
- Admin can delete and edit ads.
- Admin can choose from one of our language modules, or create his own language module.
- Specify your own colors.
- Use your own template

RobocodeNG is an Artificial Intelligence Tanks Battle Arena.

RobocodeNG is the continuation of the excelent job done by Mathew Nelson, which is the creator of Robocode.

The NG in RobocodeNG stands for Next Generation, meaning that the intension is the extend the original Robocode game with new features.

The original robocode is a game where artificially controlled tanks battle to the death in an arena. RobocodeNG Spices up the game adding better graphics, mods, guns, armors, tank bodies, etc, to introduce the great unbalance that the Robocode community needed.

RobocodeNG is based on Robocode version 1.0.7. If Mathew will ever make new versions of Robocode, we will of course make sure that RobocodeNG is updated accordingly.

Qucs project is going to be an integrated circuit simulator which means you will be able to setup a circuit with a graphical user interface (GUI) and simulate the large-signal, small-signal and noise behaviour of the circuit. After that simulation has finished you can present the simulation results on a presentation page or window.
- Qucs, briefly for Qt Universal Circuit Simulator, is a circuit simulator with graphical user interface. The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter, harmonic balance analysis, noise analysis, etc.
- Qucsator, the simulation backend, is a command line circuit simulator. It takes a network list in a certain format as input and outputs a Qucs dataset. It has been programmed for usage in the Qucs project but may also be used by other applications.
For people who are familiar with such simulators they should remember ADS from Agilent Technologies, Microwave Office from AWR and all the other simulators.
Enhancements:
- This release comes with a translation into Ukrainian, a selectable preprocessor in the SPICE component, and two new components (exponential voltage and current source).
- Libraries can now contain analogue as well as digital subcircuits.
- Analogue modelling is substantially strengthened by symbolically defined devices.
- The list of available functions in the equation solver has been extended to support more functions, logical and rational operators, and the ternary ?: construct.
- Pure digital simulations can be also performed by Verilog-HDL as an alternative to VHDL.