Free router simulator rapidshare software for linux

SIP Express Router (ser) is a high-performance, configurable, free SIP ( RFC3261 ) server .
SER features an application-server interface, presence support, SMS gateway, SIMPLE2Jabber gateway, RADIUS/syslog accounting and authorization, server status monitoring, FCP security, etc. Web-based user provisioning, serweb, available.
Its performance allows it to deal with operational burdens, such as broken network components, attacks, power-up reboots and rapidly growing user population.
SERs configuration ability meets needs of a whole range of scenarios including small-office use, enterprise PBX replacements and carrier services.
Main features:
- accounting
- digest authentication
- CPL scripts
- ENUM support
- instant messaging
- MySQL support
- PostgreSQL support
- a presence agent
- Radius authentication and accounting
- Diameter authentication
- record routing
- SMS gateway
- Jabber gateway
- NAT traversal support transaction module
- registrar
- user location
SER has been extensively and successfuly tested with many SIP products from other vendors (Microsoft, Cisco, Mitel, snom, Pingtel, Siemens, and many others). It has been powering our SIP services continuously for more than two years.

ndisc6 consists of two small command line tools (ndisc6 and rdisc6) that perform ICMPv6 Neighbor Discovery and ICMPv6 Router Discovery respectively.
NDisc6 is primarily meant for IPv6 networking diagnostics or to detect rogue IPv6 nodes or routers on an Ethernet segment.
Enhancements:
- traceroute has been parallelized for faster execution, and handles IPv6 extension headers and more ICMPv6 errors, UDP-Lite probes.
- rdisc6 supports RFC4191 (router preference and specific routes) and RDNSS.

AODV-UU (Ad-hoc On-demand Distance Vector Routing, from Uppsala University) is a routing protocol under investigation by the IETF for use in ad-hoc networks, where both end-users and routers are mobile.
AODV-UU supports IPv6 and multicasting (with the appropriate patch) and is compliant with RFC 3561.
Main features:
- Runs on Linux 2.4.x kernels and in the ns-2 simulator.
- Crosscompiling for ARM based devices like the iPAQ and Zaurus is supported.
- Complies with RFC3561
- Implemented as a user-space daemon and requires NO kernel modifications.
- Easy to compile, install and run.
- Optional unidirectional link detection and avoidance (not specified in draft).
- Multiple network interfaces support.
- (Multiple) Gateway support through tunneling.

Alliance is a complete set of free CAD tools and portable libraries for VLSI design. Alliance CAD System includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools.
A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).
Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.
Alliance provides CAD tools covering most of all the digital design flow:
- VHDL Compilation and Simulation
- Model checking and formal proof
- RTL and Logic synthesis
- Data-Path compilation
- Macro-cells generation
- Place and route
- Layout edition
- Netlist extraction and verification
- Design rules checking

Hardware::Simulator is a Perl extension for Perl Hardware Descriptor Language.

SYNOPSIS

use Hardware::Simulator;

# NewSignal( perl_variable [, initial_value]);
# create a signal called $in_clk, give it an initial value of 1
NewSignal(my $in_clk,1);

# Repeater ( time_units , code_ref)
# every time_units, call the code reference, starting at the current time
Repeater ( 5, sub{if ( $in_clk==0) { $in_clk=1;} else { $in_clk=0;}});

# Responder ( [signal_name ... signal_name], code_ref );
# respond to any changes to signals by calling code reference.
# any time out_clk changes, print value of clock and simulation time.
Responder ( $out_clk, sub
{
my $time = SimTime();
print "out_clk = $out_clk. time=$timen";
});

# start processing of events and event scheduling.
EventLoop();

Hardware::Simulator ==> a Perl Hardware Descriptor Language

Hardware::Simulator is a lightweight version of VHDL or Verilog HDL. All of these languages were developed as means to describe hardware.

Hardware::Simulator was created as a means to quickly prototype a basic hardware design and simulate it. VHDL and Verilog are both restrictive in their own ways. Hardware::Simulator was created to quickly put something together as a "proof of concept", to show that a design concept would work or not. and then the design could be translated to VHDL or Verilog.

The problem that started all of this was designing a fifo for a video scaling asic. The chip used a buffer to store incoming video data. The asic read the buffer to generate the outgoing video image. We estimated how large we thought the buffer needed to be, but we wanted to confirm that our numbers were right by running simulations.

The problem was we needed to run hundreds of different simulations, given the permutations of input image formats, output image formats, and input/output clock frequencies. We also had text files containing valid formats and frequencies. A text file as input called for perl to manipulate, split, format, and extract the data properly.

This data then had to be translated onto the a HDL simulation. The problem was that there was no easy way to write a perl script that would simulate hardware, so the only solution was to have perl drive a Verilog simulator and pass all these parameters via command line parameters. so then verilog files had to be created, and the simulator had to be driven, and the end result was a lot of work to simulate a simple fifo.

Time contraints did not allow me to develop a HDL package for perl to solve the original problem, but I took it on in my spare time. and eventually Hardware::Simulator was born.

Linux LiveCD Router project allows you to share and firewall your broadband connection and use WIFI.
You can use DSL, ADSL, Cable Modem, T1, Fixed IPs, Dial-Up, WIFI, build you own Access Point and more.
Main features:
- Share and Firewall your broadband or dedicated Internet connection
- Includes Firewall Shorewall and Masquerading (NAT)
- Does not require any installation. It is a LiveCD, your computer simply boots straight from the CD. Does not require a hard disk
- Supports DSL, Cablemodem, Fixed IP and Dial-Up
- Traffic Control, QoS
- DHCP Client and Server
- Remote SSH administration
- Includes DNS Cache to accelerate surfing
- Includes SNMP Monitoring, MRTG graphical statistics
- Use standard and low cost computer, networking and wifi hardware (also USB)
- Can use multiple ethernet and wifi 802.11a/b/g cards. Supports PCI, USB and PCMCIA cards (can replace external Access Points!)
- Linux Software compatible with Windows and Mac Networks

Quite Universal Circuit Simulator (Qucs) is an integrated circuit simulator which means you are able to setup a circuit with a graphical user interface (GUI) and simulate the large-signal, small-signal and noise behaviour of the circuit. After that simulation has finished you can view the simulation results on a presentation page or window.

The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter, Harmonic Balance analysis, noise analysis, etc.

Qucsator, the simulation backend, is a command line circuit simulator. It takes a network list in a certain format as input and outputs a Qucs dataset.

Whats New in This Release:

The new release comes with a new translation into Ukrainian, a selectable preprocessor in the SPICE file component and two new components, i.e. an exponential voltage and current source. Libraries
can now contain analogue as well as digital subcircuits. Analogue modelling is substantially strengthened by symbolically defined devices. And last but not least pure digital simulations can be also performed by Verilog-HDL as an alternative to VHDL.

In the simulation backend the equation defined devices (EDD) have been implemented as well as the two new signal sources. Also the list of
available functions in the equation solver has been extended to support vt(), hypot(), limexp(), arcsec(), arccosec(), arsech() and arcosech(). Furthermore logical and rational operators as well as the ternary ?: construct can be used in equations.