Free kitchen designs software for linux

Signs is a tool for logic synthesis and gate level simulation. Signss project main features include synthesis of RTL-style VHDL circuit descriptions and a dynamic graphical netlist viewer.
Supported formats include VHDL, ISCAS, and limited support for BLIF, Verilog, and EDIF netlists. Various true value and fault simulators and a combinational ATPG are included for circuit testing.
Aside from GUI mode, Signs has a pure command line mode and is fully scriptable in JavaScript and Ruby.
Main features:
- Written in Java, therefore platform-independent
- Aims to be VHDL93 compliant, at the moment a VHDL Subset is supported
- (Limited) support for non-synthesizable VHDL code, useful for testbenches
- Synthesis of RTL-style sequential VHDL process descriptions according to IEEE Std 1076.6
- Dynamic graphical netlist viewer supporting annotations (signal/gate names, signal values provided by simulators, faults)
- VHDL netlist output to file
- Input and output of netlists in ISCAS benchmark format
- Gate level true value simulators: event-based (any circuit), bit-parallel (combinational circuits only)
- Fault simulators: PPSFP, simple single faultsim
- Input and output of pattern lists in WGL format
- ATPG for combinational circuits: Implication-Graph based, PODEM
- Limited support for Verilog and EDIF netlists
- Fully scriptable in Rhino: JavaScript for Java and JRuby
- Pure command-line mode available besides GUI mode
- Integrated environment including source code and netlist structure tree views, build system, compilers and editors with syntax highlighting
Enhancements:
- While the release focus is clearly on bugfixes, there are also some feature improvements, such as enhanced test bench support and improved netlist and simulator views.
- The VHDL compiler has support for subprograms now and elaboration of big designs is much faster because of improved context handling.
- Internally, the intermediate representation layer was cleaned up, so intermediate objects form a proper tree now.

virtbench is a set of benchmarks for virtualization environments / hypervisors. The project is designed to be easy to run and easy to extend. The main audience will be people developing hypervisors.

The system can be used in the electronic world to keep track of your: Schematic, Printed Circuit Board, Front Plate, Programmable Logic Device numbers.
EDA index is programmed in PHP (and XHTML 1.0), using a MySQL database to store data, so its more or less OS independent, but a Linux server is recommended, since it already got most software installed as default, this configuration is also called LAMP (Linux Apache MySQL PHP)
Its also recommended that a local intranet server is used, since the system dont got a user login, so all data can be viewed without a password, but when you need to add or edit data a password is required. At first this approach might seem wierd, but its designed to allow quick lookups. Example:
You are sitting with a broken pcb with a number on it, and need to find the schematic (so you can repair it) on the computer or in the printed project (schematic) archive. EDA Index allow an quick lookup in the database, without you needing to login, so you get the job done faster.
As far as I know, there are no commercial (or free) program available that can do what EDA Index can, some companies may have created their own software, but how do that help you.
I have worked in an electronic department that had a self made application, but it lagged features like search.
This program is very usefull, if you are using numbers when:
Drawing electronic Schematics and PCBs using a CAD program like: Eagle, gEDA, Protel, Orcad, etc.
Creating Front Plate layouts in: GIMP, Coral Draw, Photoshop, AutoCAD, etc.
Programming Programmable Logic Devices like: PLD, EPLD, CPLD, PIC, APIC, PEEL, PAL, GAL, FPGA, Intel 80XX, Motorola 68XX, etc. Writing the code in: VHDL, Assambler, JEDEC, etc.
Enhancements:
- Included the bugfix to RC2.
- Updated online documentation.
- Updated INSTALL file.

Dolphin Smash is a mixed-signal, multi-language simulator for IC or PCB designs. Dolphin Smash extends its capabilities for mixed signal code-coverage and sensitivity-analysis up to detecting flaws in Virtual Testbenches and to identifying circuit weaknesses for the DfM conscious designer.
Improvement on the block-busting GUI features facilitate further the adjustments of speed versus accuracy, as well as tracing, now augmented for a hierarchical view applicable to mixed signal design.
Main features:
- Code coverage for HDL-AMS
- DC & small-signal dispersion sensitivity analysis
- Power consumption estimation after Place & Route with SPEF back-annotation
- Enhanced GUI with tree view selection of traces and interactive logging panes
- BSIM4v5 update including a well proximity effect model
- CSDF and VCD output formats for exporting of analog and logic simulation results
- VDA automotive libraries bundled
With analysis of sensitivity to dispersion, SMASH provides a fast and accurate solution for the problems of design for yield, manufacturability and robust design of nano-electronic analog circuits. Compared to Monte Carlo analysis, the sensitivity to dispersion is thousands of times faster. Furthermore, the sensitivity to dispersion analysis provides the contribution of each component to the total dispersion, thus design debugging becomes trivial.
As SCROOGE enables power consumption analysis before Place & Route, the SPEF back-annotation now provides it with parasitic capacitance back-annotation for an accurate power consumption analysis after Place & Route. Parasitic capacitances are taken into account to back-annotate the Liberty wire load model. This allows to consider the exact routing capacitance both for cell interconnection wires and for clock trees, which represent an important part of the consumed power.
For increased interoperability, simulation results can now be exported into standard VCD (Verilog Change Dump) format for logic or CSDF (Common Simulation Data Format) for reuse in all compatible EDA solutions. Of course, SMASH can also import and display VCD or CSDF results as well as.
Enhancements:
- The release delivers an interactive debugger with break points, step by step and event back trace for source level debugging of HDL-AMS descriptions, phase-noise extraction on long term Jitter, a SPICE inductance model with magnetic core as well as cosimulation of analog and mixed-signal blocks with MATLAB/Simulink.

GearHead is a mecha roguelike roleplaying game.
Set a century and a half after nuclear war, you can explore a world where various factions compete to determine the future of the human race.
Major features include random plot generation, a detailed character system, and over two hundred customizable mecha designs.
There are two things which really separate GearHead from most
other ASCII-based RPGs. First, movement is somewhat more complex.
Second, you get to pilot giant robots.
Movement in GearHead is a bit more complex than it is in most other roguelikes, but once you get used to it I hope youll enjoy it. Your character has direction, speed, and altitude. These three values are shown in the navigational display, on the left hand side of the character info window.
The display should look something like this:
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