Free hdl software for linux

Hardware::Simulator is a Perl extension for Perl Hardware Descriptor Language.

SYNOPSIS

use Hardware::Simulator;

# NewSignal( perl_variable [, initial_value]);
# create a signal called $in_clk, give it an initial value of 1
NewSignal(my $in_clk,1);

# Repeater ( time_units , code_ref)
# every time_units, call the code reference, starting at the current time
Repeater ( 5, sub{if ( $in_clk==0) { $in_clk=1;} else { $in_clk=0;}});

# Responder ( [signal_name ... signal_name], code_ref );
# respond to any changes to signals by calling code reference.
# any time out_clk changes, print value of clock and simulation time.
Responder ( $out_clk, sub
{
my $time = SimTime();
print "out_clk = $out_clk. time=$timen";
});

# start processing of events and event scheduling.
EventLoop();

Hardware::Simulator ==> a Perl Hardware Descriptor Language

Hardware::Simulator is a lightweight version of VHDL or Verilog HDL. All of these languages were developed as means to describe hardware.

Hardware::Simulator was created as a means to quickly prototype a basic hardware design and simulate it. VHDL and Verilog are both restrictive in their own ways. Hardware::Simulator was created to quickly put something together as a "proof of concept", to show that a design concept would work or not. and then the design could be translated to VHDL or Verilog.

The problem that started all of this was designing a fifo for a video scaling asic. The chip used a buffer to store incoming video data. The asic read the buffer to generate the outgoing video image. We estimated how large we thought the buffer needed to be, but we wanted to confirm that our numbers were right by running simulations.

The problem was we needed to run hundreds of different simulations, given the permutations of input image formats, output image formats, and input/output clock frequencies. We also had text files containing valid formats and frequencies. A text file as input called for perl to manipulate, split, format, and extract the data properly.

This data then had to be translated onto the a HDL simulation. The problem was that there was no easy way to write a perl script that would simulate hardware, so the only solution was to have perl drive a Verilog simulator and pass all these parameters via command line parameters. so then verilog files had to be created, and the simulator had to be driven, and the end result was a lot of work to simulate a simple fifo.

Time contraints did not allow me to develop a HDL package for perl to solve the original problem, but I took it on in my spare time. and eventually Hardware::Simulator was born.

Knoppix Elphel is a Live CD based in Knoppix 4.0.2.

This release includes new AJAX GUI (camvc) with DVR capability in addition to the earlier developed software.

Archive (LiveCD-1.5.0.build.tar) include all files, needed for build live CD/DVD manually, except original CD/DVD images. Please see build instruction in README file in archive.

Elphel, Inc. was started in 2001 to provide high performance cameras based on free software and hardware designs. Freedom of the users of Elphel products is our top priority - we value and protect it with the GNU General Public License that covers all the Elphel software and hardware designs.

[Elphel] is Software and HDL code for Elphel reconfigurable network cameras.

CA::AutoSys is a Perl interface to CAs AutoSys job control.

SYNOPSIS

use CA::AutoSys;

my $hdl = CA::AutoSys->new( [OPT] ) ;
my $jobs = $hdl->find_jobs($jobname) ;
while (my $job = $jobs->next_job()) {
:
}
my $status = $job->get_status() ;
my $children = $job->find_children() ;
while (my $child = $children->next_child()) {
:
}

CLASS METHODS

new()
my $hdl = CA::AutoSys->new( [OPT] ) ;

Creates a new CA::AutoSys object.

Below is a list of valid options:

dsn

Specify the DSN of the AutoSys database server to connect to. If nothing is specified, Sybase will be assumed: dbi:Sybase:server= With this option you should be able to connect to databases other than Sybase.

server

Specify the AutoSys database server to connect to. Either this option or the dsn option above must be given. Please note, that when specifying this server option, a Sybase database backend is assumed.

user

Specify the database user. With an out-of-the-box AutoSys installation, the default user should work.

password

Specify the database password. With an out-of-the-box AutoSys installation, the default password should work.

Example:

my $hdl = CA::AutoSys->new(server => "AUTOSYS_DEV");

Qfsm project is a graphical editor for finite state machines written in C++ using Qt the graphical Toolkit from Trolltech.
Finite state machines are a model to describe complex objects or systems in terms of the states they may be in. In practice they can used to design integrated circuits or to create regular expressions, scanners or other program code.
Main features:
- Drawing, editing and printing of diagrams
- Binary, ASCII and "free text" condition codes
- Multiple windows
- Integrity check
- Interactive simulation
- AHDL/VHDL/Verilog HDL/KISS export
- State table export in Latex, HTML and plain text format
- Ragel file export (used for C/C++, Java or Ruby code generation)
Enhancements:
- English user documentation was written.
- The possibility of default transition was introduced.
- Ragel file export was added.
- The input condition "any" was introduced.
- The possibility to invert transition conditions was introduced.
- More arrow types were added.
- The "Free Text" type was added.
- The "print header" option was added.