Free hardware platform interface software for linux

Hardware Monitor is a multi-purpose, beautiful system-monitoring applet.
The Hardware Monitor applet is an applet for the GNOME panel which tries to be a beautiful all-around solution to system monitoring. It also strives to be user-friendly and generally nice and sensible, integrating pleasantly with the rest of your GNOME desktop.
Includes different viewers, including a flame effect, allows multiple devices to be monitored in the samme applet, uses smooth updating, polished graphs, clean HIG-compliant interface.
Main features:
- A graphical view where each monitor is represented by a (time, measurement) colored curve
- A bar-plot view with a horizontal bar per monitor
- A column view with a column (time, measurement) diagram for each monitor
- A textual view which simply lists the monitors and the currently measured values
- A flame view which produces spiffy flames, the sizes of which are determined by the values of the monitored device
And the applet supports monitoring the following hardware characteristics:
- CPU usage (all CPUs, or one at the time) - niced background processes such as SETI@home are automatically ignored
- Memory usage - cache and buffers are automatically ignored
- Swap usage
- Load average
- Disk usage (or disk space free)
- Network throughput (Ethernet, wireless, modem, serial link), either incoming or outgoing or both
- Temperatures from internal sensors (e.g. system board and CPU temperatures)
- Fan speeds from internal sensors

X Hardware Monitor is a hardware monitor that shows indicators for temperature, voltage, fan speed etc, of a running system with a graphical panel.

The default configuration allows to monitor up to 3 temperatures, 3 fan speeds and 6 voltages. This tool is more particularly adequate for bi-processor systems.

Hardware::Simulator is a Perl extension for Perl Hardware Descriptor Language.

SYNOPSIS

use Hardware::Simulator;

# NewSignal( perl_variable [, initial_value]);
# create a signal called $in_clk, give it an initial value of 1
NewSignal(my $in_clk,1);

# Repeater ( time_units , code_ref)
# every time_units, call the code reference, starting at the current time
Repeater ( 5, sub{if ( $in_clk==0) { $in_clk=1;} else { $in_clk=0;}});

# Responder ( [signal_name ... signal_name], code_ref );
# respond to any changes to signals by calling code reference.
# any time out_clk changes, print value of clock and simulation time.
Responder ( $out_clk, sub
{
my $time = SimTime();
print "out_clk = $out_clk. time=$timen";
});

# start processing of events and event scheduling.
EventLoop();

Hardware::Simulator ==> a Perl Hardware Descriptor Language

Hardware::Simulator is a lightweight version of VHDL or Verilog HDL. All of these languages were developed as means to describe hardware.

Hardware::Simulator was created as a means to quickly prototype a basic hardware design and simulate it. VHDL and Verilog are both restrictive in their own ways. Hardware::Simulator was created to quickly put something together as a "proof of concept", to show that a design concept would work or not. and then the design could be translated to VHDL or Verilog.

The problem that started all of this was designing a fifo for a video scaling asic. The chip used a buffer to store incoming video data. The asic read the buffer to generate the outgoing video image. We estimated how large we thought the buffer needed to be, but we wanted to confirm that our numbers were right by running simulations.

The problem was we needed to run hundreds of different simulations, given the permutations of input image formats, output image formats, and input/output clock frequencies. We also had text files containing valid formats and frequencies. A text file as input called for perl to manipulate, split, format, and extract the data properly.

This data then had to be translated onto the a HDL simulation. The problem was that there was no easy way to write a perl script that would simulate hardware, so the only solution was to have perl drive a Verilog simulator and pass all these parameters via command line parameters. so then verilog files had to be created, and the simulator had to be driven, and the end result was a lot of work to simulate a simple fifo.

Time contraints did not allow me to develop a HDL package for perl to solve the original problem, but I took it on in my spare time. and eventually Hardware::Simulator was born.

Untangle Gateway Platform is a Linux-based network gateway with pluggable modules for network applications like spam blocking, Web filtering, anti-virus, anti-spyware, intrusion prevention, VPN, SSL VPN, firewall, and more.
- Commercial-grade open source alternative to SonicWALL and WatchGuard
- 14 integrated apps - use one or all of them
- Runs on off-the-shelf hardware
Enhancements:
- A package of 5.0.1 as a VMware Virtual Appliance has been released.

Hardware::iButton::Device is a Perl object to represent iButtons.

SYNOPSIS

use Hardware::iButton::Connection;
$c = new Hardware::iButton::Connection "/dev/ttyS0";
@b = $c->scan();
foreach $b (@b) {
print "id: ", $b->id(), ", reg0: ",$b->readreg(0),"n";
}

This module talks to iButtons via the "active" serial interface (anything using the DS2480, including the DS1411k and the DS 9097U). It builds up a list of devices available, lets you read and write their registers, etc.

The connection object is an Hardware::iButton::Connection. The main user-visible purpose of it is to provide a list of Hardware::iButton::Device objects. These can be subclassed once their family codes are known to provide specialized methods unique to the capabilities of that device. Those devices will then be Hardware::iButton::Device::DS1920, etc.

Untangle Gateway Platform is a Linux-based network gateway with pluggable modules for network applications like spam blocking, Web filtering, anti-virus, anti-spyware, intrusion prevention, VPN, SSL VPN, firewall, and more.
Enhancements:
- Bugfixes from 5.0.0-beta; this release is stable.

Hardware::Vhdl::Lexer is a Perl module that can split VHDL code into lexical tokens.

SYNOPSIS

use Hardware::Vhdl::Lexer;

# Open the file to get the VHDL code from
my $fh;
open $fh, new({ linesource => $fh });

# Dump all the tokens
my ($token, $type);
while( (($token, $type) = $lexer->get_next_token) && defined $token) {
print "# type = $type token=$tokenn";
}

Hardware::Vhdl::Lexer splits VHDL code into lexical tokens. To use it, you need to first create a lexer object, passing in something which will supply chunks of VHDL code to the lexer. Repeated calls to the get_next_token method of the lexer will then return VHDL tokens (in scalar context) or a token type code and the token (in list context). get_next_token returns undef when there are no more tokens to be read.

NB: in this documentation I refer to "lines" of VHDL code and "line" sources etc., but in fact the chunks of code dont have to be broken up at line-ends - they can be broken anywhere that isnt in the middle of a token. New-line characters just happen to be a simple and safe way to split up a file. You dont even have to split up the VHDL at all, you can pass in the whole thing as the first and only "line".