Free bottomfeeder 4.4 software for linux

TestMaker delivers a rich environment for building and running intelligent test agents that test Web-enabled applications for scalability, functionality, and performance.
TestMaker comes with a friendly graphical user environment, an object-oriented scripting language (Jython) to build intelligent test agents, an extensible library of protocol handlers (HTTPS, HTTP, SOAP, XML-RPC, SMTP, POP3, IMAP), a new agent wizard featuring an Agent Recorder to write scripts for you, a library of fully-functional sample test agents, and shell scripts to run test agents from the command line and from unit test utilities.
Enhancements:
- This release requires Java 1.5 or greater.
- It provides a workaround for servers that do not correctly implement RFC 2116 for HTTP redirect commands.
- It solves a problem in the start-up script for Windows NT and 2000 users.
- It solves bugs in the agentbase.py support library for responses with no return parameters or invalid image tags, and now allows optional parameters to set the content-type of a POST.
- It also solves a problem where XSTest ran out of memory on long running load tests.

OpenDX project gives you new control over your data...and new insights into their meaning. Yet OpenDX is easy to use because it lets you visualize data in ways youve never dreamed of--without getting bogged down in the technology.
As its name implies, OpenDX is Open Source. The license allows you to freely create, distribute, and develop visualization solutions as you see fit.
OpenDX is a uniquely powerful, full-featured software package for the visualization of scientific, engineering and analytical data: Its open system design is built on a standard interface environments. And its sophisticated data model provides users with great flexibility in creating visualizations.
With OpenDX, you can create the visualizations you want to create. OpenDX has been designed to be the place where the art of science and the science of visualization come together. Its the place where theyre combined into one powerful, flexible framework that lets you "Simply Visualize."
Enhancements:
- This release fixes numerous bugs, including some with OpenGL rendering and fixed font sizes.
- It adds features for Java Explorer and a new algorithm for generating neighbors components with irregular cubic connections.

Dasher is a zooming predictive text entry system, designed for situations where keyboard input is impractical (for instance, accessibility or PDAs).
Dasher is usable with highly limited amounts of physical input while still allowing high rates of text entry.
Dasher is Free software released under the GPL. Further documentation may be found in the Doc/ subdirectory.
Enhancements:
- Various minor bugfixes

HDLmaker is a tool for generating Verilog designs. HDLmaker simplifies the development of complex FPGA designs as well as PC Boards by performing the following tasks:
- Writes hierarchical Verilog code
- Generates retargetable IO pad rings
- Generates all of the necessary scripts and Make files
- Supports mulitlanguage projects
- Converts PCB net lists into VHDL and Verilog
- Generates SCALD and PADS PCB board netlists
- Generates Schematics in Postscript format
- Designs are portable between FPGA families and CAE tools
- Simplifies the reuse of HDL code
- Converts HDLmaker, Verilog and VHDL files into fully hyper linked HTML
Main features:
- Writes Hierarchical Verilog.
- Output can be targeted to either Verilog or VHDL (VHDL support has been deprecated).
- Supports mixed language development.
- Generates PC board netlists in both PADS PCB and SCALD formats.
- Generates Schematics in Postscript format.
- Supports the most popular FPGAs
- Xilinx Virtex4,Virtex2P, Virtex2,VirtexE,Virtex, Spartan3, Spartan2,4000E,4000EX,4000XL,5200,9500, Altera Stratix
- Supports the most popular synthesizers
- Synplify
- Xilinx XST
- Altera
- Synopsys Design Compiler
- Precision
- Supports most simulators
- Fintronics Finsim
- Cadence Verilog XL
- Cadence NC-SIM
- Model Technologies (VHDL and Verilog)
- Synopsys VCS
- HTML Generation
- HDLmaker generates an HTML version of the design with hyper links from all source files to generated files and from all component instances to the components module. Verilog and VHDL HTMLized are also syntax colored.
Enhancements:
- insert_compare, Inserts a module with a compare wrapper around it
- Added HDLMAKER_ALLOW_SUB variable
- Added xst_directive
- Floorplanning support for Multipliers and Block RAMs
- New XST constraints
- Improved DDR IO support including differential DDR
- Improved Xilinx project support
- Virtex4 Support
- Better ModelSim support. Creates three command files, foo_compile_mt.cmd to compile the modules, foo_i_mt.cmd for interactive use, and foo_batch_mt.cmd for batch simulation.
- Initial values of HDLmaker variables can be passed in from the command line or from a file
- Better comment support
- More flexible #clock statement
- Comments in pin files
- Support for Xilinx ISE 6.1
- Support for Virtex2P
- Support for Precision and ModelSim added
- Large Project Support, HDLMaker now operates across multiple directories
- Virtex2, Spartan2 and Spartan2E support added
- Altera Stratix support added
- Multilanguage project support. Can embed VHDL entities into Verilog files and Verilog modules into VHDL files.