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Verilog::CodeGen 0.9.4

Verilog::CodeGen 0.9.4

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Verilog::CodeGen 0.9.4 Ranking & Summary

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User Review: 0 (0 times)
File size: 0.018 MB
Platform: Any Platform
License: Perl Artistic License
Price:
Downloads: 823
Date added: 2007-08-20
Publisher: W. Vanderbauwhede

Verilog::CodeGen 0.9.4 description

Verilog::CodeGen module is a Verilog code generator.

SYNOPSIS

use Verilog::CodeGen;

mkdir DeviceLibs/Objects/YourDesign, 0755;
chdir DeviceLibs/Objects/YourDesign;

# if the directory YourDesign exists, the second argument can be omitted
# create YourModule.pl in YourDesign
&create_template_file(YourModule,YourDesign);

# create a device library for testing in DeviceLibs/Objects/DeviceLibs
&make_module(YourModule,YourDesign);

# create the final device library in DeviceLibs (once YourModule code is clean)
&make_module(,YourDesign);

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Verilog::CodeGen 0.9.4 Copyright

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