Verilog::CodeGen 0.9.4

Verilog::CodeGen module is a Verilog code generator.

SYNOPSIS

use Verilog::CodeGen;

mkdir DeviceLibs/Objects/YourDesign, 0755;
chdir DeviceLibs/Objects/YourDesign;

# if the directory YourDesign exists, the second argument can be omitted
# create YourModule.pl in YourDesign
&create_template_file(YourModule,YourDesign);

# create a device library for testing in DeviceLibs/Objects/DeviceLibs
&make_module(YourModule,YourDesign);

# create the final device library in DeviceLibs (once YourModule code is clean)
&make_module(,YourDesign);