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sp_preproc 1.280

sp_preproc 1.280

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sp_preproc 1.280 Ranking & Summary

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User Review: 0 (0 times)
File size: 0.10 MB
Platform: Any Platform
License: Perl Artistic License
Price:
Downloads: 879
Date added: 2007-05-30
Publisher: Wilson Snyder

sp_preproc 1.280 description

sp_preproc is a SystemPerl Preprocessor.

SYNOPSIS

sp_preproc

sp_preproc takes a .sp (systemperl) file and creates the SystemC header and C files.

It is generally only executed from the standard build scripts.

ARGUMENTS

--help

Displays this message and program version and exits.

--hier-only

Read only hierarchy information, ignore all signal information. Useful for faster generation of sp_lib files.

--inline

Edit the existing source code "inline". Similar to the Verilog-mode AUTOs. Use --inline --noautos to remove the expanded automatics.

--libfile

Filename to write a list of sp_cells into, for later use as a --libcell to another sp_preproc run.

--libcell

Files listed before --libcell will be preprocessed or inlined as appropriate. Files after noexpand will only be used for resolving references, they will not be linked, linted, or otherwise checked. --nolibcell can be used to re-enable checking of subsequent files.

--ncsc

Create output files compatible with Cadence NC-SystemC.

--nolint

Disable lint style error checks, such as required to run doxygen on the SystemPerl output.

--preproc

Preprocess the code, writing to separate header and cpp files.

--trace-duplicates

Include code to trace submodule signals connected directly to a parent signal, generally for debugging interconnect. Without this switch such signals will be presumed to have the value of their parent modules signal, speeding and compressing traces.

--tree filename

Write a report showing the design hierarchy tree to the specified filename. This format may change, it should not be parsed by tools.

--noautos

With --inline, remove any expanded automatics.

--verbose

Shows which files are being written, or are the same.

--write-verilog filename

Write the SystemC interconnections in Verilog format to the specified filename. Note this does not include logic, it only contains module ports and cells.

-M

Makes the dependency listing (similar to cpp -M).

-Dvar=value

Sets a define to the given value (similar to cpp -D).

-f file

Parse parameters from the given file.

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sp_preproc 1.280 Copyright

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