Hardware::Simulator 0000_0005

Hardware::Simulator is a Perl extension for Perl Hardware Descriptor Language.

SYNOPSIS

use Hardware::Simulator;

# NewSignal( perl_variable [, initial_value]);
# create a signal called $in_clk, give it an initial value of 1
NewSignal(my $in_clk,1);

# Repeater ( time_units , code_ref)
# every time_units, call the code reference, starting at the current time
Repeater ( 5, sub{if ( $in_clk==0) { $in_clk=1;} else { $in_clk=0;}});

# Responder ( [signal_name ... signal_name], code_ref );
# respond to any changes to signals by calling code reference.
# any time out_clk changes, print value of clock and simulation time.
Responder ( $out_clk, sub
{
my $time = SimTime();
print "out_clk = $out_clk. time=$timen";
});

# start processing of events and event scheduling.
EventLoop();

Hardware::Simulator ==> a Perl Hardware Descriptor Language

Hardware::Simulator is a lightweight version of VHDL or Verilog HDL. All of these languages were developed as means to describe hardware.

Hardware::Simulator was created as a means to quickly prototype a basic hardware design and simulate it. VHDL and Verilog are both restrictive in their own ways. Hardware::Simulator was created to quickly put something together as a "proof of concept", to show that a design concept would work or not. and then the design could be translated to VHDL or Verilog.

The problem that started all of this was designing a fifo for a video scaling asic. The chip used a buffer to store incoming video data. The asic read the buffer to generate the outgoing video image. We estimated how large we thought the buffer needed to be, but we wanted to confirm that our numbers were right by running simulations.

The problem was we needed to run hundreds of different simulations, given the permutations of input image formats, output image formats, and input/output clock frequencies. We also had text files containing valid formats and frequencies. A text file as input called for perl to manipulate, split, format, and extract the data properly.

This data then had to be translated onto the a HDL simulation. The problem was that there was no easy way to write a perl script that would simulate hardware, so the only solution was to have perl drive a Verilog simulator and pass all these parameters via command line parameters. so then verilog files had to be created, and the simulator had to be driven, and the end result was a lot of work to simulate a simple fifo.

Time contraints did not allow me to develop a HDL package for perl to solve the original problem, but I took it on in my spare time. and eventually Hardware::Simulator was born.